Instruction generation for cache resident self test of processors
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1
Instruction generation for cache resident self test of processors (2009)
~EN PB NWISBN: 9783639193756 bzw. 363919375X, vermutlich in Englisch, VDM, Taschenbuch, neu.
Lieferung aus: Deutschland, Lieferbar in 2 - 3 Tage.
Targeting both stuck-at and delay faults in processors and SOCs With delay defects becoming more common due to the properties of the newer process technologies, at- speed functional tests have become indispensable. Traditionally, functional tests needed expensive automatic testing equipment due to the memory and speed requirements associated. This cost issue was solved by native-mode (or cache resident) testing which uses the intelligence of the processor to test itself. In the native-mode self-test (also known as software-based self-test) paradigm, instruction sequences are loaded into the cache (and also made cache resident) to test the processor for defects. Generally, only random instructions are used in native mode tests. As with any random sequence based testing, there are faults that are left undetected by random instructions. Manual effort is necessary to generate the tests that can detect those faults, requiring a detailed knowledge of the instruction set architecture and the micro-architecture of the processor. In this book, an automatic technique is proposed that alleviates the need for such manual effort. 01.09.2009, Taschenbuch.
Targeting both stuck-at and delay faults in processors and SOCs With delay defects becoming more common due to the properties of the newer process technologies, at- speed functional tests have become indispensable. Traditionally, functional tests needed expensive automatic testing equipment due to the memory and speed requirements associated. This cost issue was solved by native-mode (or cache resident) testing which uses the intelligence of the processor to test itself. In the native-mode self-test (also known as software-based self-test) paradigm, instruction sequences are loaded into the cache (and also made cache resident) to test the processor for defects. Generally, only random instructions are used in native mode tests. As with any random sequence based testing, there are faults that are left undetected by random instructions. Manual effort is necessary to generate the tests that can detect those faults, requiring a detailed knowledge of the instruction set architecture and the micro-architecture of the processor. In this book, an automatic technique is proposed that alleviates the need for such manual effort. 01.09.2009, Taschenbuch.
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Instruction generation for cache resident self test of processors (2009)
DE PB NW RPISBN: 9783639193756 bzw. 363919375X, in Deutsch, VDM Verlag Sep 2009, Taschenbuch, neu, Nachdruck.
Von Händler/Antiquariat, AHA-BUCH GmbH [51283250], Einbeck, Germany.
This item is printed on demand - Print on Demand Titel. Neuware - With delay defects becoming more common due to the properties of the newer process technologies, at- speed functional tests have become indispensable. Traditionally, functional tests needed expensive automatic testing equipment due to the memory and speed requirements associated. This cost issue was solved by native-mode (or cache resident) testing which uses the intelligence of the processor to test itself. In the native-mode self-test (also known as software-based self-test) paradigm, instruction sequences are loaded into the cache (and also made cache resident) to test the processor for defects. Generally, only random instructions are used in native mode tests. As with any random sequence based testing, there are faults that are left undetected by random instructions. Manual effort is necessary to generate the tests that can detect those faults, requiring a detailed knowledge of the instruction set architecture and the micro-architecture of the processor. In this book, an automatic technique is proposed that alleviates the need for such manual effort. 148 pp. Englisch.
This item is printed on demand - Print on Demand Titel. Neuware - With delay defects becoming more common due to the properties of the newer process technologies, at- speed functional tests have become indispensable. Traditionally, functional tests needed expensive automatic testing equipment due to the memory and speed requirements associated. This cost issue was solved by native-mode (or cache resident) testing which uses the intelligence of the processor to test itself. In the native-mode self-test (also known as software-based self-test) paradigm, instruction sequences are loaded into the cache (and also made cache resident) to test the processor for defects. Generally, only random instructions are used in native mode tests. As with any random sequence based testing, there are faults that are left undetected by random instructions. Manual effort is necessary to generate the tests that can detect those faults, requiring a detailed knowledge of the instruction set architecture and the micro-architecture of the processor. In this book, an automatic technique is proposed that alleviates the need for such manual effort. 148 pp. Englisch.
3
Instruction generation for cache resident self test of processors
DE PB NWISBN: 9783639193756 bzw. 363919375X, in Deutsch, Vdm Verlag Dr. Müller, Taschenbuch, neu.
Lieferung aus: Deutschland, Versandkostenfrei.
buecher.de GmbH & Co. KG, [1].
With delay defects becoming more common due to the properties of the newer process technologies, at- speed functional tests have become indispensable. Traditionally, functional tests needed expensive automatic testing equipment due to the memory and speed requirements associated. This cost issue was solved by native-mode (or cache resident) testing which uses the intelligence of the processor to test itself. In the native-mode self-test (also known as software-based self-test) paradigm, instruction sequences are loaded into the cache (and also made cache resident) to test the processor for defects. Generally, only random instructions are used in native mode tests. As with any random sequence based testing, there are faults that are left undetected by random instructions. Manual effort is necessary to generate the tests that can detect those faults, requiring a detailed knowledge of the instruction set architecture and the micro-architecture of the processor. In this book, an automatic technique is proposed that alleviates the need for such manual effort.2009. 148 S.Versandfertig in 3-5 Tagen, Softcover.
buecher.de GmbH & Co. KG, [1].
With delay defects becoming more common due to the properties of the newer process technologies, at- speed functional tests have become indispensable. Traditionally, functional tests needed expensive automatic testing equipment due to the memory and speed requirements associated. This cost issue was solved by native-mode (or cache resident) testing which uses the intelligence of the processor to test itself. In the native-mode self-test (also known as software-based self-test) paradigm, instruction sequences are loaded into the cache (and also made cache resident) to test the processor for defects. Generally, only random instructions are used in native mode tests. As with any random sequence based testing, there are faults that are left undetected by random instructions. Manual effort is necessary to generate the tests that can detect those faults, requiring a detailed knowledge of the instruction set architecture and the micro-architecture of the processor. In this book, an automatic technique is proposed that alleviates the need for such manual effort.2009. 148 S.Versandfertig in 3-5 Tagen, Softcover.
4
Instruction generation for cache resident self test of processors
DE NWISBN: 9783639193756 bzw. 363919375X, in Deutsch, VDM Verlag Dr. Müller, Saarbrücken, Deutschland, neu.
Lieferung aus: Deutschland, zzgl. Versandkosten, Sofort lieferbar.
Targeting both stuck-at and delay faults in processors and SOCs, Targeting both stuck-at and delay faults in processors and SOCs.
Targeting both stuck-at and delay faults in processors and SOCs, Targeting both stuck-at and delay faults in processors and SOCs.
5
Symbolbild
Instruction generation for cache resident self test of processors (2009)
DE PB NW RPISBN: 9783639193756 bzw. 363919375X, in Deutsch, VDM Verlag Dr. Müller, Saarbrücken, Deutschland, Taschenbuch, neu, Nachdruck.
Von Händler/Antiquariat, English-Book-Service - A Fine Choice [1048135], Waldshut-Tiengen, BW, Germany.
This item is printed on demand for shipment within 3 working days.
This item is printed on demand for shipment within 3 working days.
6
Symbolbild
Instruction generation for cache resident self test of processors (2009)
DE PB NW RPISBN: 9783639193756 bzw. 363919375X, in Deutsch, VDM Verlag Dr. Müller, Saarbrücken, Deutschland, Taschenbuch, neu, Nachdruck.
Von Händler/Antiquariat, English-Book-Service - A Fine Choice [1048135], Waldshut-Tiengen, Germany.
This item is printed on demand for shipment within 3 working days.
This item is printed on demand for shipment within 3 working days.
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